Use of Ion Implantation in Semiconductor Processing
Very great improvements in the scale of integration of semiconductor devices on integrated circuit (IC) chips and the speed of operation of such devices have been achieved over the past several years. These improvements have been made possible by a number of advances in integrated circuit manufacturing equipment as well as improvements in the materials and methods utilized in processing virgin semiconductor wafers into IC chips. The most dramatic advances in manufacturing equipment have been improved apparatus for lithography and etching and improved systems for implanting ions of conductivity modifying impurities into the semiconductor wafer.
Generally, the density of integrated circuits and their speed of operation are dependent largely upon the accuracy and resolution of the lithography and etching apparatus used to form patterns of circuit elements in masking layers on the semiconductor wafer. However, density and speed are also dependent upon tight control of the profile of doped regions in the wafer, i.e., regions to which substantial concentrations of conductivity modifying impurities have been added. Tight control of wafer doping can best be achieved using ion implantation techniques and equipment.
Large scale integration (LSI) and very large scale integration (VLSI) of conductor-insulator-silicon (CIS) devices are improved by making more efficient use of the wafer area, shortening interconnects between devices, producing smaller geometries and reducing noise. All of these improvements are made possible in large part through the use of ion implantation doping methods.
Manufacture of bipolar circuits has also been improved with ion implantation. In this processing technology, improvements have resulted from performing predepositions with ion implantation and simultaneously taking advantage of the low contamination and compatibility with photoresist masking which are characteristics of ion implantation equipment.
It is well-known in the industry that doping small geometric regions of a semiconductor wafer cannot be done adequately with gaseous or spin-on deposition of the dopant material on the surface of the wafer, followed by a high temperature furnace diffusion operation which drives the dopant material into the semiconductor wafer in an isotropic manner, i.e., the dopant molecules travel laterally as well as vertically into the wafer. The kinds of dopant profiles, concentrations and lateral geometries required on an LSIC or VLSIC wafer make ion implantation the doping process of choice. The uniformity of doping achievable only with ion implantation is critical in the fabrication of smaller geometry devices. In addition, doping uniformity across the wafer and repeatability from wafer to wafer, which is achievable with ion implantation, dramatically improves fabrication yields of high density devices.